1. Field of the Invention
The invention relates to a method of fabricating a dynamic random access memory (DRAM), and more particularly to a method of fabricating a DRAM capacitor.
2. Description of the Related Art
A dynamic random access memory cell, normally called a memory cell, includes a transistor and a capacitor. The capacitor is used to store a bit of data in a memory device. Data storage for DRAM selectively charges or discharges each capacitor in the capacitor array on a semiconductor substrate. For a capacitor with a fixed operative voltage, the capacitance of the capacitor is decided by the surface area of the capacitor electrode when the thickness and the dielectric constant of the capacitor dielectric layer are both fixed.
The size of DRAM cell is gradually reduced as the integration of integrated circuits is continuously increased. It is well known by people skilled in the art that the capacitance of the capacitor is decreased since its size is reduced. The decreased capacitance easily causes soft errors by .alpha. rays, which results in a data storage failure in the memory cells.
Therefore, a capacitor structure with high integration and capacitance is required, thereby keeping a desired capacitance under the circumstances in which the size of the capacitor is reduced to make possible a DRAM with high capacitance and good performance.
FIGS. 1A-1C shows cross-sectional views illustrating fabrication of a stacked DRAM capacitor according to prior art. Referring to FIG. 1, a field oxide layer 12 used to isolate the active areas is formed on a semiconductor substrate 10. A transistor composed of a gate oxide layer 14, a gate electrode 16 and a source/drain region 18, 20 is formed on the substrate 10. An insulating layer 22 is then formed over the substrate 110 and patterned to form a contact window 23 within the insulating layer 22 to expose the source/drain region 18.
Referring to FIG. 1B, a conductive layer 24 is formed and fills the contact window 23 to electrically connect to the source/drain region 18. The conductive layer 24 is used to serve as a lower electrode of DRAM capacitor. Thereafter, a capacitor dielectric layer 26 and a conductive layer 28 are successively formed on the conductive layer 24, as shown in FIG. 1C, to achieve a stacked capacitor.
As shown in FIG. 1C, a portion of the lower electrode 24 expands onto the insulating layer 22 to increase its surface area. However, since the density of the device is increased, the range of the lower electrode 24 cannot expand as widely as possible. Accordingly, the capacitance of the capacitor is decreased.